ESP32 firmware v0.8.17 — experimental C5 support

Adds an experimental ESP32-C5 headless firmware bundle alongside S3/C6, guarded C5 installation, and user/build guides. C5's bootloader is at 0x2000; select the matching bundle and verify both archive and image checksums.

Fixed

• Prevents legacy mmWave GPIO17/18 probing from rerouting the C5 flash/PSRAM bus. Unconfigured C5 sensor probes are skipped; explicit pins are checked against memory and console assignments.
• Flash qualification and the public SDK monitor reject watchdog/flash-busy evidence even if initial CSI callbacks appear.
• C5 writes require production-chip identity, sufficient flash and esptool >=5.3.
• Updates libz-sys for RUSTSEC-2026-0418; bounds harness test concurrency for Windows helper startup.

Real hardware evidence and limits

MEASURED (bounded real hardware; reproducer in the linked record): Production ESP32-C5HR8 revision 1.2 with 8 MB flash was backed up, installed and provisioned. Corrected firmware 0.8.17 booted and streamed real CSI without captured watchdog/flash-busy errors in bounded captures. The production SDK receiver decoded all 971 packets in its recorded sample with no malformed or unknown packets.

Cadence was AP-dependent: recorded raw CSI samples were roughly 12?29 packets/s. Bounded extra traffic did not produce a consistent improvement. This setup did not consistently meet the 20 packets/s acceptance target. C5 remains experimental; this is not a sensing-accuracy, comparative speedup or long-run reliability qualification.

Profile: 2.4 GHz, 240 MHz CPU, 8 Hz edge DSP, 4 MB OTA layout, UART console. Display, WASM and PSRAM are disabled. 5 GHz is not qualified. Exact board form factor remains operator-unconfirmed; the generic profile has no LED or default sensor pin assignment.

References

• Firmware/install changes: #2382
• SDK monitor and measured documentation: #2389
• Cadence follow-up: #2388
• Setup checklist: https://gist.github.com/ruvnet/bacfc5ac6b4feed7cfc1f76c03d12f4c
• Full record: https://github.com/ruvnet/RuView/blob/main/docs/validation/2026-10-28-esp32-c5-candidate.md

Firmware bundles must come from the green tag workflow. Verify downloads against SHA256SUMS.txt before flashing. Preserve credentials and full flash backups privately.

Publication verification

Firmware release workflow https://github.com/ruvnet/RuView/actions/runs/40915261010 completed successfully after removing an empty duplicate staging draft. All four final archives passed outer/inner checksums and embedded version/chip checks. The C5 bundle matched the exact CI artifact and the images installed on COM8. An anonymous download returned HTTP 200 with a matching checksum.

The final release-image check decoded all 479 received packets, including 371 raw CSI frames, with no unknown or malformed packets; the public serial monitor also passed. A separate five-minute corrected-firmware run decoded all 5,318 packets, including 4,197 raw CSI frames, without captured firmware faults or disconnects. Cadence remains AP-dependent and below target in some runs.

Harness 0.9.3 is not yet published to npm: CI passed tests and packaging but registry authorization was rejected. Use the checked-out main source installer for C5 support meanwhile. Publisher access is tracked at #2390 . No workstation npm publish was attempted.

MEASURED compatibility with the previous server image

The real C5 on released firmware also passed a live test against ghcr.io/ruvnet/wifi-densepose:v0.8.16-esp32 (revision 3686bc7): health HTTP 200, unauthenticated API HTTP 401, authenticated API HTTP 200, C5 node active and its CSI sequence advancing. The temporary container was stopped after the test. This is software/transport compatibility evidence, not a matched ESP32 hardware-performance comparison or sensing-accuracy qualification. Local API requests used a direct loopback connection; the host HTTP proxy had caused the first health probe to time out.