riscv/riscv-isa-manual riscv-isa-release-c6deaea-2026-04-24

Release riscv-isa-release-c6deaea-2026-04-24

on GitHub

This release was created by: aswaterman
Release of RISC-V ISA, built from commit c6deaea, is now available.

What's Changed

• Update documentation for menvcfg and menvcfgh registers by @davidharrishmc in #2977
• Clarify mip and mie register implementation and WARL field requirements by @davidharrishmc in #2974
• Clarify wording in misa register documentation by @davidharrishmc in #2973
• Zacas: Tweak by @omasanori in #2971
• Tweak by @omasanori in #2970

Full Changelog: riscv-isa-release-8bde8c4-2026-04-24...riscv-isa-release-c6deaea-2026-04-24