This release was created by: aswaterman
Release of RISC-V ISA, built from commit ba52a8a, is now available.
What's Changed
- Added WARL norm rules only declared in wavedrom reg layouts and those missing impl-def-behavior = true property by @james-ball-qualcomm in #2707
- LR_SC_ALIGNMENT now identified as a impldef and combined for misaligned load/store impldefs into one by @james-ball-qualcomm in #2712
Full Changelog: riscv-isa-release-8cf4af7-2026-02-28...riscv-isa-release-ba52a8a-2026-03-04