riscv/riscv-isa-manual riscv-isa-release-3720f4e-2026-04-13

Release riscv-isa-release-3720f4e-2026-04-13

on GitHub

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 3720f4e, is now available.

What's Changed

• Clarify which Smdbltrp SRET behaviors are qualified by M-mode by @aswaterman in #2871

Full Changelog: riscv-isa-release-f020df5-2026-04-11...riscv-isa-release-3720f4e-2026-04-13