github riscv/riscv-cheri v0.9.9-ar20260810

4 hours ago

Release with small clarifications following v0.9.9-ar20260707

  • Clarified behaviour of rs1=x0 for LY/SY in integer mode (PR #1166). This was not clearly specified before, now calling out that it behaves exactly the same way as LB/LH/LW/LD/etc.
  • Changing sstatus.YRGE requires SFENCE.VMA (PR #1176). Previously it was not clearly defined whether it takes effect immediately or requires the fence.
  • The capability bounds decoding correction factors section wording was made easier to read and a new clarification diagram added (PR #1169 and PR #1177)
  • Plus a few small wording/formatting fixes

All other changes are to non-v1.0 content such as the H extension and the Debug specification.

Full autogenerated PR changelog:

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Full Changelog: v0.9.9-ar20260707...v0.9.9-ar20260810

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