20260707 Release for ARC review with minor review feedback changes compared to 0.9.8.2
Changes since v0.9.8.2
Architectural changes, in response to ARC / Summit feedback:
- YSENTRY is now part of the RVY base ISA; the separate Zysentry extension is
removed. Its encoding changed: the source operand is now rs2, and rs1 must be x0
(reserved for a future YSEAL instruction taking an authorizing capability in rs1). - The Y (CHERI enable) bit in menvcfg/senvcfg moved from bit 28 to bit 8.. The previous 0x1c was a placeholder, move to next available bit for final freeze.
- misa.Y now resets to 1 and completely disables CHERI when cleared. Clearing
is only permitted while all implicit-check CSRs (pc, xtvec, xepc, and ddc with
Zyhybrid) hold root capabilities; otherwise the write is ignored. (Previously
misa.Y reset to 0 and only gated the per-mode enables.) - Renamed the capability encoding format to "RV64LYA" (was
RV64LYmw14rc1ps), and "sentry" is expanded to "sealed entry point" throughout.
Otherwise:
- The RV64LYA metadata layout is rearranged so that the AP, SDP and GL fields each have adjacent reserved space for future growth (bit positions of SDP, AP, P and GL changed).
- This also fixes a bug in the SC.Y description that now correctly states that rd is set to zero on success (instead of 1). This was correct in the attach sail code, but typo'd in the description.
- The debug specification is now in a separate document. Optional capability-width abstract command support has been added to it.
All other changes are non-functional: grammar and clarification fixes, restructured
bounds-decoding and CSR sections, improved tables/diagrams/cross-references, and
corrections of unclear/misleading documentation.
Full autogenerated PR changelog:
- Bump actions/download-artifact from 7 to 8 by @dependabot[bot] in #1042
- Explanation around progbuf sequences to access capabilities by @JanMatCodasip in #1040
- DRET clarification by @tariqkurd-repo in #1045
- Fix typos in Sdext section by @JanMatCodasip in #1046
- PMA clarification by @tariqkurd-repo in #1047
- Rename M->P by @tariqkurd-repo in #1049
- improve cap dirty tracking wording by @tariqkurd-repo in #1062
- Minor documentation fixes by @tariqkurd-repo in #1065
- Improve YSS description by @tariqkurd-repo in #1060
- Use "widens" instead of "extends to" by @arichardson in #1070
- Clarify that illegal AP states are reserved for RV64Y by @tariqkurd-repo in #1064
- Bump actions/checkout from 6 to 7 by @dependabot[bot] in #1072
- misa.y can only be disabled if ddc/pcc are root caps by @tariqkurd-repo in #1058
- Simplify encoding name by @tariqkurd-repo in #1061
- representable region -> representable range everywhere by @tariqkurd-repo in #1075
- Move YSENTRY into the base and rename it by @tariqkurd-repo in #1066
- Remove outdated reference to a future unseal instruction by @Flowdalic in #1073
- JALR: Fix AsciiDoc formatting for the {cs1} placeholder by @Flowdalic in #1074
- Fix parameter chapter, Zyhybrid definition and RV32 chapter by @tariqkurd-repo in #1071
- Put Y in Xenvcfg bit 9 by @tariqkurd-repo in #1078
- Priv spec review by @tariqkurd-repo in #1077
- instruction page fixes by @tariqkurd-repo in #1079
- Tidy up appendix by @tariqkurd-repo in #1081
- Add defn of subset and simplify description of Zylevels1 by @tariqkurd-repo in #1080
- Fix review feedback by @tariqkurd-repo in #1082
- restructuring the document and fixing review feedback by @tariqkurd-repo in #1084
- Add table headings so that page breaks are less confusing by @tariqkurd-repo in #1087
- Improve metadata field arrangement by @tariqkurd-repo in #1089
- YSEAL -> YSENTRY by @tariqkurd-repo in #1088
- small review fixes by @tariqkurd-repo in #1090
- encode part of AP field for RV64Y by @tariqkurd-repo in #1091
- Continued review by @tariqkurd-repo in #1092
- minor fixes by @tariqkurd-repo in #1093
- Tidy debug chapter by @tariqkurd-repo in #1094
- Fix RV64LYA encoding format diagram by @tariqkurd-repo in #1095
- Debug integration review by @JanMatCodasip in #1069
- add MISA reset note by @tariqkurd-repo in #1096
- Improve multiple-root text for writing caps through abstract commands by @tariqkurd-repo in #1098
- User mode CSR summary was missing by @tariqkurd-repo in #1099
- fix misa/Xenvcfg/pc reset values by @tariqkurd-repo in #1097
- Document tidy from separating debug chapter by @tariqkurd-repo in #1102
- Avoid using a separate AP_CMP field by @arichardson in #1100
- Fix rvy_instruction_encodings.py to label ymodesw correctly by @arichardson in #1104
- Fix table heading that used wrong funct3 code by @arichardson in #1105
- Separate out debug spec by @tariqkurd-repo in #1101
- Fix Claude feedback by @tariqkurd-repo in #1103
- revert to 1-bit per permission by @tariqkurd-repo in #1107
- Add rationale on legalisation with enableL8 by @PeterRugg in #1106
- Clarify the misa.Y text and move the write behaviour to that section by @arichardson in #1109
- Make p depends on x into a rule by @tariqkurd-repo in #1108
- Fix AP note by @tariqkurd-repo in #1111
- Clarify reset values by @tariqkurd-repo in #1110
- Fix pytest by @arichardson in #1115
- Appendix A: add ARC-NOTE on encoding formats and fix headings by @arichardson in #1114
- Spec review fixes by @arichardson in #1112
- Trivial proofreading fixes by @arichardson in #1116
- Remove redundant "Included in::" field from instruction listings by @arichardson in #1113
- Describe C.ADDI16SP/C.ADDI4SPN by deferring to YADDI by @arichardson in #1118
- Describe the menvcfg/senvcfg Y bit and link its definition by @arichardson in #1120
- Fix SC.Y success/failure value in description by @arichardson in #1121
- Fixes for the CMO chapter by @arichardson in #1119
- Slim down the mode-naming ARC-NOTE by @arichardson in #1122
- Spell out that BEQ/BNE with rs1=rs2 is reserved by @arichardson in #1125
- SC.Y return value now matches unpriv by @tariqkurd-repo in #1127
- Put xstatus diagrams in correct places by @tariqkurd-repo in #1128
- Clarify YPERMR result when integrity checks fail by @arichardson in #1124
- Add back sail snippets by @arichardson in #1117
- separate mandatory and optional integrity checks by @tariqkurd-repo in #1123
- Encoding format fixes by @tariqkurd-repo in #1129
- Add BNE/BEQ into RVY modified instructions by @tariqkurd-repo in #1130
- Add multiple anchors into sections by @tariqkurd-repo in #1131
- Fix AP_MAX value by @tariqkurd-repo in #1132
- Convert leftover editorial notes into ARC-NOTEs by @arichardson in #1133
- Drop stale suggested assembly syntax from YADD/YADDI by @arichardson in #1134
- Specify that SRLIY encodings with shamt != XLEN are reserved by @arichardson in #1135
- Reword AP-field encoding legality statement by @arichardson in #1136
- Fix tag note on YMODEW by @arichardson in #1137
- Remove stale branch-execution wording from capability checks by @arichardson in #1138
- Avoid undefined mode terminology in the Zca chapter opening by @arichardson in #1139
- Fix mangled JALR Operation listing by @arichardson in #1140
- Rephrase the manual sail note by @arichardson in #1141
- Fix inverted EF values in the malformedLSB note by @arichardson in #1142
- Shrink the placeholder-references section by @arichardson in #1145
- Fix misleading mode-observation explanation by @arichardson in #1146
- Bump NEXT_VERSION to v0.9.9 by @arichardson in #1152
- Clarify Load Capability Fault conditions by @arichardson in #1147
- Note why the YTYPER Sail reads the sealed boolean by @arichardson in #1149
- Remove stale two-register phrasing from mtvec by @arichardson in #1150
- Explain why YBNDSRW sail checks rs1 instead of rounded bounds by @arichardson in #1148
- Tidy the cap bounds decoding section by @tariqkurd-repo in #1143
- Align the PMA SC.Y tag-store-fault rule with dirty tracking by @arichardson in #1151
- Another round of minor specification review fixes by @arichardson in #1126
- Make misa.y=0 condition implementation defined by @tariqkurd-repo in #1144
Full Changelog: v0.9.8.2...v0.9.9-ar20260707