Notable changes in the RISC-V CHERI specification since v0.9.7.1

These changes were made based on ARC review feedback on the previous version:

New Opcode Allocation:
- Relocated instruction encodings from the standard RISC-V opcode space to formerly Custom space. Custom1-3 become reserved for RVY when the base ISA is RVY, all new instructions are in what is Custom-3 for RVI.
- Change the immediate format of YBNDSWI
- Added scripts to generate Sail, QEMU, and riscv-opcodes clauses, and new appendices for encoding overviews and standalone documentation references.
Clarified Hybrid Mode:
- Hybrid Mode Rewrite: Substantially cleaned up the hybrid mode definition and now use the name P-bit (instead the M-bit) for controlling pointer modes
- Zyhybrid is now defined as an extension on top of the RVY base ISA rather than RVI, maintaining identical functionality while aligning with the new encoding structure (cannot be based on RVI otherwise RVY opcode space would be custom).
- Added a new appendix detailing intended hybrid usage models.
Zylevels1 (Local/Global) Rewrite: Substantially refactored the Zylevels1 chapter to simplify it and add usage examples.
Further ARC Review Updates:
- Integration of the YBLD and YTOPR instructions into the base ISA to avoid single-instruction extensions.
- Fixed name of YLT (it's an inclusive subset not a less than) to use YSS (for subset)
- Many other smaller improvements based on ARC feedback (full list of changes below).

Spec changes

Specify remapping of custom space by @tariqkurd-repo in #1019
ARC review updates and includes renaming hybrid modes and M-bit->P-bit by @tariqkurd-repo in #1006
Move YBLD into the base by @tariqkurd-repo in #1005
Fix description and rename YLT to YSS and SYEQ to YEQ by @tariqkurd-repo in #1001
put YTOPR into the base by @tariqkurd-repo in #998
simplify JALR/Sentry text for RV64 by @tariqkurd-repo in #994
Update for new instruction encodings in Custom-3 by @arichardson in #1002

Fix YTOPR description by @tariqkurd-repo in #997
Postpone Zylevels1 by @tariqkurd-repo in #995
fix typo by @tariqkurd-repo in #1004
Reword to clarify that load LM permission clearing is based on written back tag by @PeterRugg in #1009
fix ARC comments on unpriv ISA section by @tariqkurd-repo in #1010
Subset of PR 1006 - ARC review comments by @tariqkurd-repo in #1011
Use set to 0 instead of cleared consistently by @arichardson in #1015
Drop redundant sentence by @arichardson in #1017
Move Zca table by @arichardson in #1016
Avoid mixing ABI names and numbers by @arichardson in #1014
Refactor the Zylevels1 chapter by @arichardson in #1018
Add an appendix describing Zyhybrid usage models by @arichardson in #1013
Reinstate Zylevels1 in the non-full build by @arichardson in #1020
A few minor clarifications by @arichardson in #1022
Use pointers instead of addresses in the CSR classes by @arichardson in #1021
RV64->RV64Y, RV32->RV32Y by @tariqkurd-repo in #1024
FIX: Avoid accidental HTML <em> tags in PlantUML diagrams. by @DaveMcEwan in #1023
Add simple text clarifying utid by @PeterRugg in #1025
Update HTML links in the README by @arichardson in #1026
Minor formatting fix for YBNDSWI by @arichardson in #1027
Omit redundant changelog section from default build by @arichardson in #1028
Fix a few minor typos by @arichardson in #1029

Full Changelog: v0.9.7.2...v0.9.8