riscv/riscv-cheri v0.9.3-prerelease

on GitHub

Spec changes

• Use stval/stval2 for HS-mode exceptions, not htval/htval2 by @jrtc27 in #483
• Split CRG functionality for U and S-modes by @tariqkurd-repo in #491
• specify M-bit behaviour when there's no integer mode by @tariqkurd-repo in #507

Clarifications

• fix issue 504, purecap clarifications by @tariqkurd-repo in #505
• Made it clear that tid(c) registers refer to software threads by @francislaus in #486
• clarify PTE fault exception priority, and add into instruction pages by @tariqkurd-repo in #485
• clarify invalid address handling for address + 4 x HICAUSE when writing to MTVECC by @tariqkurd-repo in #489
• clarify element zero exceptions for FoF loads by @tariqkurd-repo in #487
• clarify PCC fault vs instruction access fault by @tariqkurd-repo in #495
• clarify FoF loads by @tariqkurd-repo in #500
• clarify CSRs which are only added if hybrid mode is implemented by @tariqkurd-repo in #503

Typos

• amo: amoswap: offset must be 0 by @martin-kaiser in #499

Intrastructure updates

• Bump docs-resources from a76dd1d to 62576cd by @dependabot in #492
• Remove support for downloading CSVs from Google Docs by @Timmmm in #497
• Add initial support for Sail snippets by @Timmmm in #498

New Contributors

• @jrtc27 made their first contribution in #483

Full Changelog: v0.9.2-prerelease...v0.9.3-prerelease