This release was created by: arichardson
Release of RISC-V ISA, built from commit daebb9d, is now available.
Full Changelog: riscv-isa-release-96fd1c3-2025-05-23...riscv-isa-release-daebb9d-2025-05-23
What's Changed
- Minor wording fix for mtvecc vectored check by @tomaird in #538
- Fix encoding of C.FSD instruction by @tomaird in #537
- Update contributors. by @pmundkur in #539
- Update specifications status to "Stable" by @arichardson in #541
- Bump docs-resources from
62576cdto1d5bcd2by @dependabot[bot] in #543 - fix typo in rep range section by @tariqkurd-repo in #546
- Improve consistency of CSR descriptions by @arichardson in #544
- Update for ratified spec: Zilsd, Zclsd by @tariqkurd-repo in #545
- Clarify CHERI PTE fault priority when 2-stage translation is in use by @tariqkurd-repo in #547
- Revert MXLEN to XLEN in RV memory description by @andresag01 in #532
- make M-bit dependent on X for RV64 by @tariqkurd-repo in #550
- Add note about PTW by @tariqkurd-repo in #553
- making c.addi16sp/c.addi4spn more consistent with the RISC-V arch spec by @tariqkurd-repo in #554
- CSR cleanup by @tariqkurd-repo in #556
- Clarify scbndsr rounding by @PeterRugg in #560
- If CRE=0, PTE bits are reserved by @tariqkurd-repo in #559
- do mtvecc rep check with MODE field zeroed by @tariqkurd-repo in #542
- small fixes by @tariqkurd-repo in #563
- remove PTE bits being reserved by @tariqkurd-repo in #564
- fix major opcode label for SH4ADD.UW by @tariqkurd-repo in #570
- rep range clarifications by @tariqkurd-repo in #567
- add note about ACPERM without Zcherilevels by @tariqkurd-repo in #569
- minor fix to c.scsp by @tariqkurd-repo in #573
- Initial integration with ISA manual by @arichardson in #566
- Clarify CHERI page fault dependence on PTE.U by @Timmmm in #576
- ARC feedback on unpriv by @tariqkurd-repo in #584
- Attempt to create consistency regarding commas around e.g. and i.e. by @francislaus in #585
- clean up cap instruction page section, and some other improvements by @tariqkurd-repo in #586
- fix amoswap.c defn by @tariqkurd-repo in #598
- clean up spec of LC/SC/LR.C/SC.C by @tariqkurd-repo in #596
- instruction page readability improvements by @tariqkurd-repo in #595
- fix ifdef syntax by @tariqkurd-repo in #599
- reapply changes from PR 600 by @tariqkurd-repo in #604
- clarify implicit ACPERM behaviour by @tariqkurd-repo in #590
- Minor consistency improvements by @francislaus in #591
- Revert back to requiring whole-line bounds for CBO.INVAL by @jrtc27 in #607
- rework unpriv CSR section by @tariqkurd-repo in #602
- improvements to readability by @tariqkurd-repo in #610
- Making zstid part of the main CHERI extension by @francislaus in #588
- set LVLBITS=1 and give the option of increasing it in future by @tariqkurd-repo in #611
- reorganize and simplify CSR accesses, and extensive unpriv proofreading by @tariqkurd-repo in #612
New Contributors
Full Changelog: v0.9.5...riscv-isa-release-daebb9d-2025-05-23