This release was created by: arichardson
Release of RISC-V ISA, built from commit d1c9e92, is now available.
What's Changed
- zyhybrid: clarify role of rs1 in (Non-CHERI) Address Mode by @Flowdalic in #850
Full Changelog: riscv-isa-release-0283e87-2025-11-14...riscv-isa-release-d1c9e92-2025-11-18