This release was created by: tariqkurd-repo
Release of RISC-V ISA, built from commit c80f2d4, is now available.
What's Changed
- In int mode cap load/stores can have rs1=x0 by @tariqkurd-repo in #1166
- Multiple non-normative updates in debug document by @JanMatCodasip in #1162
Full Changelog: riscv-isa-release-81ac4b7-2026-07-15...riscv-isa-release-c80f2d4-2026-07-16