This release was created by: arichardson
Release of RISC-V ISA, built from commit c5fe37d, is now available.
What's Changed
- Bump NEXT_VERSION to v0.9.9 by @arichardson in #1152
- Clarify Load Capability Fault conditions by @arichardson in #1147
- Note why the YTYPER Sail reads the sealed boolean by @arichardson in #1149
- Remove stale two-register phrasing from mtvec by @arichardson in #1150
- Explain why YBNDSRW sail checks rs1 instead of rounded bounds by @arichardson in #1148
Full Changelog: riscv-isa-release-dc334a2-2026-07-07...riscv-isa-release-c5fe37d-2026-07-07