This release was created by: tariqkurd-repo
Release of RISC-V ISA, built from commit c32b27d, is now available.
What's Changed
- Clarify debugger code sequences by @tariqkurd-repo in #1311
- RV32Y: fix SL permission so it's only granted if W is granted by @tariqkurd-repo in #1305
- Clarify priority of PTE faults in algorithm by @arichardson in #1293
- Clarify xenvcfg.Y read-only behavior when misa.Y=0 by @arichardson in #1308
- int mode for root cap was missing since 0.9.3 by @tariqkurd-repo in #1296
- add note about cheri state with misa.y=0 by @tariqkurd-repo in #1294
- Copy Sdtrig into the standalone cheri spec so it is submitted for ARC review by @tariqkurd-repo in #1310
Full Changelog: riscv-isa-release-b889e5c-2026-11-05...riscv-isa-release-c32b27d-2026-11-06