riscv/riscv-cheri riscv-isa-release-ac8df5d-2025-04-15 on GitHub

This release was created by: arichardson
Release of RISC-V ISA, built from commit ac8df5d, is now available.

What's Changed

Minor wording fix for mtvecc vectored check by @tomaird in #538
Fix encoding of C.FSD instruction by @tomaird in #537
Update contributors. by @pmundkur in #539
Update specifications status to "Stable" by @arichardson in #541
Bump docs-resources from 62576cd to 1d5bcd2 by @dependabot in #543
fix typo in rep range section by @tariqkurd-repo in #546
Improve consistency of CSR descriptions by @arichardson in #544
Update for ratified spec: Zilsd, Zclsd by @tariqkurd-repo in #545
Clarify CHERI PTE fault priority when 2-stage translation is in use by @tariqkurd-repo in #547
Revert MXLEN to XLEN in RV memory description by @andresag01 in #532
make M-bit dependent on X for RV64 by @tariqkurd-repo in #550
Add note about PTW by @tariqkurd-repo in #553
making c.addi16sp/c.addi4spn more consistent with the RISC-V arch spec by @tariqkurd-repo in #554
CSR cleanup by @tariqkurd-repo in #556
Clarify scbndsr rounding by @PeterRugg in #560
If CRE=0, PTE bits are reserved by @tariqkurd-repo in #559
do mtvecc rep check with MODE field zeroed by @tariqkurd-repo in #542
small fixes by @tariqkurd-repo in #563
remove PTE bits being reserved by @tariqkurd-repo in #564
fix major opcode label for SH4ADD.UW by @tariqkurd-repo in #570
rep range clarifications by @tariqkurd-repo in #567
add note about ACPERM without Zcherilevels by @tariqkurd-repo in #569
minor fix to c.scsp by @tariqkurd-repo in #573
Initial integration with ISA manual by @arichardson in #566

Full Changelog: v0.9.5...riscv-isa-release-ac8df5d-2025-04-15