Added
- stream_to_mem: Allows to use memories with flow control (req/gnt) for requests but
without flow control for output data to be used in streams. - isochronous_spill_register: Isochronous clock domain crossing cutting all paths.
rr_arb_tree_tb: Systemverilog testbench forrr_arb_tree, which checks for fair throughput.cf_math_pkg::idx_width: Constant function for defining the binary representation width
of an index signal.
Changed
addr_decode: Usecf_math_pkg::idx_widthfor computing the index width, inline documentation.lzc: Usecf_math_pkg::idx_widthfor computing the index width, inline documentation.Bender: Change levels of modules affected by depending oncf_math_pkg::idx_width().stream_xbar: Fully connected stream bassed interconnect with variable number of inputs and outputs.stream_xbar: Fully connected stream-bassed interconnect with a variable number of inputs and outputs.
Fixed
- Improve tool compatibility.
rr_arb_tree: Properly degeneraterr_iandidx_osignals.rr_arb_tree: Add parameterFairArbto distribute throughput of input requests evenly when
not all inputs have requests active.stream_demux: Properly degenerateinp_sel_isignal.