Changes since 0.4.5

Added

• Add axi channel delayer

Changed

• Remove clock from AXI_BUS and AXI_LITE. Such a clock signal is useful for testing purposes
  but confusing (or even harmful) in hardware designs. For testing purposes, the AXI_BUS_DV and
  AXI_LITE_DV (suffix for "design verification") interfaces have been defined instead.

Fixed

• Update src_files.yml to match Bender.yml.
• Add missing axi_test to compile script.