Changes since 0.22.1
Added
axi_lite_regs: Add memory-mapped registers with AXI4-Lite slave port and the option to make individual bytes read-only.
Changed
- Interfaces
AXI_LITEandAXI_LITE_DV: addaw_protandar_protsignals.- The
AXI_LITE_ASSIGN*andAXI_LITE_SET*macros (ininclude/axi/assign.svh) have been updated to include the two new interface signals. axi_test::axi_lite_driver: A newprotfunction argument has been added to thesend_aw,send_ar,recv_aw, andrecv_arfunctions.axi_test::rand_axi_lite_master:- A new
w_protandr_protfunction argument has been added to thewriteandreadfunction, respectively. The new arguments have a default value of'0. - The
send_awsand thesend_arsfunction now randomizes theprotsignal of each AW and AR, respectively.
- A new
axi_test::rand_axi_slave: Displayprotsignal (but otherwise still ignore it).
- The
Fixed
rand_axi_master(inaxi_test): Another fix to respect burst type restrictions when emitting ATOPs.