This release contains an important TLS fix for ARM along with a few
minor compatibility fixes
-
Make __aeabi_read_tp respect ARM ABI register requirements to
avoid clobbering register contents during TLS variable use. -
Use cpu_family instead of cpu in meson config, which is 'more
correct' when building for a single cpu instead of multilib. -
Make arm sample interrupt vector work with clang
-
Use __inline instead of inline in published headers to allow
compiling with -ansi -
Make 'naked' RISC-V _start function contain only asm
statements as required by clang (and recommended by gcc). -
Use -msave-restore in sample RISC-V cross-compile
configuration. This saves text space.