Changes/Fixes from 0.03RC2
- SW: Improved profiling attacks with basic example in documentation
- SW: Analysis software now uses a 'master script', simplifies doing custom stuff along with development, not fully documented yet
- SW: Improves preprocessing modules, adds decimation and clock recovery modules
- SW: Detects and displays changes in project file when closing
- SW: Project file editor
- FPGA: Fixed timing error with SAD trigger
- FPGA: Fixes to USI Interface allow use with SmartCard
- FPGA: Glitch has mode where can hold output high for several cycles
- FPGA: Glitch has single-shot mode using external trigger
- DOC: Several new tutorials
Before Running Please Note
- Check documentation (linked above) for install information
- Run self.clearAllSettings() in python console if you are installing this to a DIFFERENT directory than your existing installation
Known Issues (Critical Only)
- Project files mostly DO NOT work. Does not save analysis results (analyzer) or hardware settings (capture). Only item saved is trace data.
- Cannot open a project file once you've already got one open, must close project and reopen software.
- Many things cause crashes.