Fixed Issues / Improvements
- Fix bugs in image/sampler tracking to properly track argument when compiling with -cl-opt-disable
- Move pass to erase redundant movs after other optimizations are done.
- Skip simd32 compilation for per-pixel dispatch with x16 samples.
- Revert new-reg-per-function behavior in VC RA
- Add new Relocation Type R_PER_THREAD_PAYLOAD_OFFSET_32 Also refactor vISA::RelocationEntry create API
- Moving IntrinsicGenISA.gen to build Config folder and adding proper dependency requirement
- Switch to using LLVMTargetMachine in VC. Initialized GenX pass in BackendPlugin.
- Add check for fp64 and i64 copy move if platform does not support 64b types.
- Program the correct response length for spill of a scalar variable used as send dst.
- Enable FP64 accumulator as mul instruction source.
- Add TGL emulation functions for DP and SP
- DWARF debugger location expressions
- Emit variable location off privateBase
- additional include guards to avoid re-defintion conflict of LARGE_INTEGER type
- Uniform analysis tuning for performance.
- For stack calls do not adjust the spill size by global scratch offset
- Relocations and symbols support in L0 binary in VC
- Update register numbering for debug info.
- Try to avoid bank conflict for Gen12 when scheduling
- Fix some excessive mov instructions emitted by VectorCompiler.
- Avoid unncessary llvm metadata regenerations to optimize compilation time
Ubuntu 18.04 binary packages for LLVM10/Clang10 are included.