eclipse-threadx/threadx v6.5.1.202602

Eclipse ThreadX 6.5.1.202602 Release Notes

This release expands hardware platform support with major RISC-V improvements — including three new boards and the addition of support for the RISC-V Vector Extension (RVV) — and introduces native Win64 ports for both ThreadX and ThreadX SMP. It also delivers a significantly updated Xtensa port, QEMU-based automated CI forRISC-V, and several bug fixes for Cortex-M and RISC-V targets.

We thank contributors from 10xEngineers, Alibaba, Bradford Space, Cadence Design Systems, JBLopen, Quintauris, Taktflow Systems, and Volz Servos for their valuable contributions to this release.

Vulnerabilities addressed

No new vulnerabilities were addressed in this release. You can access advisories for previously addressed vulnerabilities here.

Highlights

RISC-V Expanded Support

This release includes the most significant expansion of RISC-V support to date:

RVV (Vector Extension): The RISC-V 64-bit architecture port and the qemu_virt example now support the RISC-V Vector Extension (RVV). (#508, @goodnorning)
Port consolidation: The RV32 and RV64 ports have been refactored and consolidated for maintainability. Toolchain files have been cleaned up (riscv32-unknown-elf, riscv-none-elf-rv32imc for xPack users). (#536, #537, #539, @fdesbiens)
Performance: Lazy FPU save/restore and GP relaxation have been implemented for the GNU RISC-V 32-bit port.(#513, @Winstonllllai)
Bug fixes: A critical bug where MPIE was cleared after an mret instruction — causing interrupts to be permanently disabled — has been fixed. (#522, @cpdpls) A misalignment issue caused by an incorrect ULONG size definition has also been corrected. (#534, @cpdpls)

New RISC-V Hardware Platforms

Three new platforms are now supported:

Bananapi BPI-F3 (SpacemiT K1 SoC) BSP (#531, @akifejaz)
OpenHW CORE-V MCU platform port (#535, @fdesbiens)
OpenHW CVA6 (RISC-V 32-bit) (#511, @francisco-merino-quintauris)

New Win64 Port

ThreadX and ThreadX SMP now have native Windows 64-bit (Win64) ports, enabling development and testing on modern 64-bit Windows systems. (#529, @fdesbiens)

Xtensa Improvements

The Xtensa port has been updated with contributions from the Cadence foss-xtensa fork, including: (#525, @ianstcdns)

LX8 support for more than 32 interrupts
Context switch logic fixes
Interrupt fixes for TX_ENABLE_EXECUTION_CHANGE_NOTIFY
Support for __DYNAMIC_REENT__
Execution profiling support

QEMU-based CI for RISC-V

Automated regression test infrastructure using QEMU has been added for both RV32 and RV64. (#526, @akifejaz)

Other Bug Fixes

Fixed race condition and message loss in Cortex-M GNU ports (#523, @fdesbiens)
Fixed SysTick initialisation in tx_initialize_low_level.s (#278, @Polarisru)
Fixed incorrect -mcpu=cortex-a9 link flag (#273, @hodcarrier)
Removed duplicate invalidateCaches_IS declaration (#273, @hodcarrier)
Fixed incorrect default value of TX_TIMER_TICKS_PER_SECOND in tx_user_sample.h (#521, @jblanchard-jblopen)

Build System

Added conditional CMake support for ThreadX SMP (#524, @fdesbiens)
Fixed THREADX_ARCH undefined when building ThreadX as a standalone CMake library (#540, @fdesbiens)

New Contributors

@jblanchard-jblopen made their first contribution in #521
@MrNetic made their first contribution in #270
@hodcarrier made their first contribution in #273
@Polarisru made their first contribution in #278
@howjmay made their first contribution in #361
@nhuvaoanh123 made their first contribution in #514
@cpdpls made their first contribution in #522
@ianstcdns made their first contribution in #525
@Winstonllllai made their first contribution in #513

Full Changelog: v6.5.0.202601_rel...v6.5.1.202602_rel

eclipse-threadx/threadx v6.5.1.202602_rel Eclipse ThreadX v6.5.1.202602 on GitHub