cyring/CoreFreq 2.0.5

v2.0.5

on GitHub

[Code Review]

• Restrict module parameters to load-time only

[AMD]

[Genoa]

• Attempt SOC voltage reading
• Apply monitoring interval to RAM consumption calculation

[Kernel]

• Use CONFIG_AMD_NB to call SMU if kernel version ≥ 6.0

[Intel]

[Core Ultra]

• Updated register names and addresses

[Alder Lake/N]

• Added "Twin Lake" and "Amston Lake" codenames

[x86_64]

• Added lock prefix to bit operations for cross-package atomicity

[AArch64] [RISC-V] [PowerPC]

• Improved CPU topology detection to identify the BSP (Boot Strap Processor)

CoreFreq ISO

SHA1 of the attached image

37f1134e92b7216f523434863a257c791d146a47