cyring/CoreFreq 1.95.2

v1.95.2

on GitHub

[UI]

• Fixed the aggregation of the minimum ratio

[Intel]

• [Airmont][Silvermont] Attempt to decode tCKE from DRMC register
• [Airmont] Improve tWTPr, B2B, tWWDR timings
• [Airmont] Provide a new IMC decoder
• Add the Emerald Rapids architecture entry
• [DDR5][DDR4] Add the RCDw IMC timing
• [Raptor Lake ] De-activate the MSR Uncore counter

[AMD]

• "Zen3/Barcelo-R" and "Zen3+ Rembrandt-R" codenames
• [Zen] Thermal highest limit reset fix

[Misc]

• Code review and Registers documentation:
  AMD HWCR,
  Intel HDC and DRP
  Can build with Intel MSR_ANY_CORE_C0