Highlights

• The SPARC module was updated to LLVM-18 (please see the Release Guide for details).
• Python bindings now use ABI3 wheels.
• Added support for Apple's proprietary AArch64 instructions.
• Instructions that can be decoded but are invalid for other reasons are now marked as such (#2707).

Note about published Python Wheels

The Alpha5 Python packages on PyPi were published by accident with commit 5d989a4 of PR #2765.
The build is equivalent to tag 6.0.0-Alpha5, except for the additions to Changelog.md.
Because Changelog.md is not part of the distributed Python wheels, we didn't republish the packages.
Sorry for any inconvenience.

What's Changed

• Apple AArch64 proprietary by @Rot127 in #2692
• Add jump group for generic jirl by @jiegec in #2698
• LoongArch: Compute absolute address for address operand by @jiegec in #2699
• Fix LoongArch ld/st instructions register info by @jiegec in #2701
• ARM: fix typo, cspr -> cpsr by @jiegec in #2716
• Fix arm pop reg access by @jiegec in #2718
• Fix missing sp register read in ret instruction by @jiegec in #2719
• Fix missing operand for smstart, due to space replaced by tab by @jiegec in #2720
• Add flag for the SoftFail case of the LLVM disassembler. by @Rot127 in #2707
• Remove unused files. by @Rot127 in #2709
• clang-format: change license to BSD-3-Clause by @tmfink in #2724
• Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type by @jiegec in #2721
• Make SStream respect the CS_OPT_UNSIGNED flag. by @Rot127 in #2723
• Make assertion hit warnings optional in release builds. by @Rot127 in #2729
• Update source list before installing valgrind. by @Rot127 in #2730
• Add x30 implicit read to the RET alias. by @Rot127 in #2739
• Print immediate only memory operands for AArch64. by @Rot127 in #2732
• Add warning about naive search and replace to patch reg names. by @Rot127 in #2728
• Enable to generate legacy MC tests for the fuzzer. by @Rot127 in #2733
• Auto-Sync update Sparc LLVM-18 by @Rot127 in #2704
• Python binding: Use ABI3 wheels by @Antelox in #2742
• Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 by @Rot127 in #2705
• Fix for Risc-V C.SRLI decoding (issue #2731) by @h01G3r in #2745
• HPPA fix mem operands access and instruction printing by @R33v0LT in #2746
• Handle zero case of R1 operand field by @Rot127 in #2743
• Fix comisd memory operand size: xmmword -> qword by @jiegec in #2750
• Fix missing repne for movsd op by @jiegec in #2752
• Explain more details about CC change. by @Rot127 in #2753
• Add a test for FCC conditions for none FPU instructions. by @Rot127 in #2758
• Print register access type and registers accessed in cstool_mips.c by @jiegec in #2762
• Fix duplication of memory operand by @Rot127 in #2761
• Python binding: Windows ARM64 build by @Antelox in #2760
• Implement cs_regs_access for Alpha architecture by @jiegec in #2763
• Fix decoding of the FCC fields of FBPcc (format 2_3). by @Rot127 in #2764

New Contributors

• @h01G3r made their first contribution in #2745

Full Changelog: 6.0.0-Alpha4...6.0.0-Alpha5