Changelog:
r43969 | oldwoman37 | 2023-06-05 23:22:36 +0000 (Mon, 05 Jun 2023) | 21 lines
The memory lookup tables are now built on the value in register 0 of the MMU.
Take the MMU value:
bit 7 : Expansion (A17 when in 256K mode)
bit 6 : A16
bit 5-4: ROM HIGH (00=ROM,01=INT,10=EXT,11=RAM)
bit 3-2: ROM MID (00=ROM,01=INT,10=EXT,11=RAM)
bit 1 : ROM LO (0=ROM,1=RAM)
bit 0 : I/O (0=I/O,1=CHARGEN)
This config starts at entry 32 (NUM_CONFIG64). This was done as C64 carts
assume base of c64 configurations are at 0. There is now better
accommodations for 256K configurations.
The monitor has been fixed so that you can properly peek (SFX off) into any
c128 bank for both CPUs.
The monitor will also switch based on the current CPU.
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r43968 | oldwoman37 | 2023-06-05 23:16:32 +0000 (Mon, 05 Jun 2023) | 1 line
Fixed comal 128 ROM addressing; works _mostly_, but circulating ROM dump is incomplete.
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r43967 | oldwoman37 | 2023-06-05 23:13:03 +0000 (Mon, 05 Jun 2023) | 1 line
Fixed -initbreak reset so that the first instruction doesn't run; this is now a temporary break and not a trap.
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r43966 | oldwoman37 | 2023-06-05 23:09:06 +0000 (Mon, 05 Jun 2023) | 1 line
x128 properly starts with Z80 and then transfers control to 8502; also fixed double reset on non-sc cores
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r43965 | pottendo | 2023-06-05 20:34:36 +0000 (Mon, 05 Jun 2023) | 2 lines
FLAG2 delay cycle is now a define (3 seems to be the best value).
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