Changelog:
r43445 | rhialto | 2023-03-07 19:43:47 +0000 (Tue, 07 Mar 2023) | 2 lines
Change tabs to spaces...
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r43444 | rhialto | 2023-03-07 19:35:45 +0000 (Tue, 07 Mar 2023) | 22 lines
More restructuring of CIA emulation: interrupt control, flags and masks.
Similar to the previous restructuring of the shift register, now introduce
a "delay line" for the ICR. Separate various actions (asserting the interrupt,
setting the high bit in the ICR ("interrupts active"), acknowledging
interrupts (i.e. resetting their flags)) in separate actions which can
be set to occur soon in the future. They can also be cancelled before they are
due. When the CIA is accessed in consecutive cycles, such as with a RMW
instruction, the intermediate stages can be observed.
This fixes the dd0dtest from the testbench.
There are 3 areas of logic involved here:
when reading from the ICR, when writing to the ICR, and "every cycle".
Fortunately, most of the time the "every cycle" code doesn't have anything to
do. The complication is on the other hand to make it run exactly once for every
cycle when it is needed. This is in particular the case when an interrupt
is about to occur, and briefly after that.
The main code for the 3 areas is strongly inspired by Hoxs64:
https://github.com/davidhorrocks/hoxs64/blob/master/hoxs64/cia6526.cpp
but delay bits have been renamed and renumbered. Instead of all events counting
up, here events scheduled for the future count down to 0.
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r43443 | compyx | 2023-03-07 18:59:22 +0000 (Tue, 07 Mar 2023) | 3 lines
Gtk3: Settings: remove "peripherals" -> "ethernet" from xplus4, copy/paste error probably
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r43439 | blackystardust | 2023-03-07 16:05:31 +0000 (Tue, 07 Mar 2023) | 1 line
Squashed some spaces.
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r43437 | blackystardust | 2023-03-07 15:55:59 +0000 (Tue, 07 Mar 2023) | 1 line
Fixed x128 z80 in/out from/to 0000-0fff in bank 0 according to real hw test results.
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